Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV

As noted previously, TSMC’s 7 nm node will be used by tens of companies for hundreds of chips targeting different applications. Initially, the company plans to offer two versions of the manufacturing technology: one for high-performance, and one for mobile applications, both of which will use immersion lithography and DUV. Moreover, eventually TSMC intends to introduce a more advanced 7nm fabrication process that will use EUV for critical layers, taking a page from GlobalFoundries’ book (which is set tp start 7 nm with DUV and then introduces second-gen 7 nm with EUV).

TSMC’s first-generation CLN7FF will enter risk production in Q2 2017 and will be used for over a dozen of tape outs this year. It is expected that high-volume manufacturing (HVM) using the CLN7FF will commence in ~Q2 2018, so, the first “7-nm” ICs will show up in commercial products in the second half of next year. When compared to the CLN16FF+, the CLN7FF will enable chip developers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60% or increase frequency by 30% (at the same complexity).

The second-generation 7 nm from TSMC (CLN7FF+) will use EUV for select layers and will require developers to redesign EUV layers according to more aggressive rules. The improved routing density is expected to provide ~10-15-20% area reduction and enable higher performance and/or lower power consumption. In addition, production cycle of such chips will get shorter when compared to ICs made entirely using DUV tools. TSMC plans to start risk production of products using its CLN7FF+ in Q2 2018 and therefore expect HVM to begin in H2 2019.

Advertised PPA Improvements of TSMC's CLN7FF Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  7FF
vs
16FF+
7FF
vs
10FF
7FF EUV
vs
7FF
5FF EUV
vs
7FF EUV
Power 60% <40% 10% lower
Performance 30% ? lower higher
Area Reduction 70% >37% ~10-15-20% tangible
HVM Start ~Q2 2018 - ~H2 2019 ~H2 2020

As it turns out, all three leading foundries (GlobalFoundries, Samsung Foundry and TSMC) all intend to start using EUV for select layers with their 7 nm nodes. While ASML and other EUV vendors need to solve a number of issues with the technology, it looks like it will be two years down the road before it will be used for commercial ICs. Of course, certain slips are possible, but looks like 2019 will be the year when EUV will be here. In fact, keeping in mind that both TSMC and Samsung are already talking about their second-gen EUV technologies (which they call 5 and 6 nm) that will use more EUV layers, it looks like the foundries are confident of the ASML TwinScan NXE manufacturing tools (as well as of the Cymer light source, pellicles, photoresists, etc.) they are going to use.

10 nm: Samsung Is Shipping, TSMC Is Steady Beyond 10 nm at Samsung: 8 nm and 6 nm
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  • SuperMecha - Saturday, May 6, 2017 - link

    “First of all, neither he, or anyone else outside those companies actually knows enough about the actual chips to know the true density.”

    That’s grossly false. Their customers (i.e. AMD, Nvidia, Qualcomm, etc.) need to have the PDKs to design their chips. The PDKs will contain the design rules and ultimately the transistor specifications necessary to design a chip for that process. TSMC will be accepting 7nm tape outs this quarter which means the transistor specifications were likely frozen some time ago. Never mind the fact that the companies have released details of their future process nodes.
    Reply
  • Wilco1 - Sunday, May 7, 2017 - link

    I guess you also don't believe then that both TSMCs and GF's 16/14nm processes are already denser than Intel's 14nm? See eg. http://www.anandtech.com/show/11170/the-amd-zen-an... Apple A8 on 20nm was shown to be much denser than Core M on 14nm.

    Whatever the marketing claims say, Intel is already behind on density in actual designs. Intel's latest 14nm process is even less dense. So what makes you think that Intel could catch up?
    Reply
  • melgross - Wednesday, May 10, 2017 - link

    Because what you're saying is wrong. I haven't read anything saying that intels's process is less dense. Reply
  • Wilco1 - Thursday, May 11, 2017 - link

    Well the link I provided shows it very clearly - I presume you didn't read it?

    Intel may have better CPP/MP/FP/SRAM at 14nm vs TSMC/GF, but AMD still gets better L2 and L3 density despite the less advanced process. And density on real designs matters more than the process marketing numbers (which are about bragging rights, but don't tell the whole story).
    Reply
  • lefty2 - Sunday, May 7, 2017 - link

    Scott's analysis was actually spot on. Dick James of TechInsights actually measured Samsungs 10nm chip: https://twitter.com/Siliconicsdick/status/85632866...
    measuring a 68 mm contacted gate pitch, 51 nm metal pitch, dual STI and single dummy gate.
    That's compared to Intel's 14nm of 70 nm CPP x 52 nm MMP

    By comparison: Intel's 14nm is 70 nm CPP x 52 nm MMP.
    Reply
  • sc14s - Friday, May 5, 2017 - link

    Seems to me past 2025 or so what are they going to do to compete assuming you hit that ~5nm and then iterate a few times on that process to maximize it's potential?
    You can't really go any further without some major physics breakthrough. it's kinda a race to the bottom just in a physics sense instead of the financial price slashing sense.
    Reply
  • melgross - Friday, May 5, 2017 - link

    Most of the work has been with carbon nanotubes, with both IBM and Hp showing progress. But it's not expected to go commercial (if ever, really) before the mid 2020s, or possibly (more likely), the later part of the decade.

    So there will be a gap. Software developers will need to improve their software to improve performance finally, which should be a big benefit for everything.
    Reply
  • bji - Friday, May 5, 2017 - link

    Regular hardware speed increases have allowed more software to be produced across a broader range of products more quickly because developers don't have to spend their time optimizing for performance as much because the hardware gets them to a 'good enough' place easily. Once the hardware is not getting faster, for every problem that requires greater performance, you simply shift more of the cost of creating the product to the software side. It will take longer to produce programs as a result. There is no free lunch; it's not like software development could have for no extra cost added more performance and now that hardware stops increasing in speed software development will just start adding that free performance in. The cost of producing software will just go up for that segment of the software market that is performance sensitive. Of course, quite a lot of the market is not performance sensitive so there will be little appreciable impact on most of the software market. Reply
  • tarqsharq - Friday, May 5, 2017 - link

    It would be quite the time to be a skilled software developer though.

    A next generation John Carmack? Using computing tricks to pull off things that traditionally would bog down the available hardware?
    Reply
  • vladx - Friday, May 5, 2017 - link

    You're assuming that there are real solutions that could revolutionize software performance and scalability, just like the P versus NP problem we might never get an answer to that. Reply

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