Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV

As noted previously, TSMC’s 7 nm node will be used by tens of companies for hundreds of chips targeting different applications. Initially, the company plans to offer two versions of the manufacturing technology: one for high-performance, and one for mobile applications, both of which will use immersion lithography and DUV. Moreover, eventually TSMC intends to introduce a more advanced 7nm fabrication process that will use EUV for critical layers, taking a page from GlobalFoundries’ book (which is set tp start 7 nm with DUV and then introduces second-gen 7 nm with EUV).

TSMC’s first-generation CLN7FF will enter risk production in Q2 2017 and will be used for over a dozen of tape outs this year. It is expected that high-volume manufacturing (HVM) using the CLN7FF will commence in ~Q2 2018, so, the first “7-nm” ICs will show up in commercial products in the second half of next year. When compared to the CLN16FF+, the CLN7FF will enable chip developers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60% or increase frequency by 30% (at the same complexity).

The second-generation 7 nm from TSMC (CLN7FF+) will use EUV for select layers and will require developers to redesign EUV layers according to more aggressive rules. The improved routing density is expected to provide ~10-15-20% area reduction and enable higher performance and/or lower power consumption. In addition, production cycle of such chips will get shorter when compared to ICs made entirely using DUV tools. TSMC plans to start risk production of products using its CLN7FF+ in Q2 2018 and therefore expect HVM to begin in H2 2019.

Advertised PPA Improvements of TSMC's CLN7FF Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  7FF
vs
16FF+
7FF
vs
10FF
7FF EUV
vs
7FF
5FF EUV
vs
7FF EUV
Power 60% <40% 10% lower
Performance 30% ? lower higher
Area Reduction 70% >37% ~10-15-20% tangible
HVM Start ~Q2 2018 - ~H2 2019 ~H2 2020

As it turns out, all three leading foundries (GlobalFoundries, Samsung Foundry and TSMC) all intend to start using EUV for select layers with their 7 nm nodes. While ASML and other EUV vendors need to solve a number of issues with the technology, it looks like it will be two years down the road before it will be used for commercial ICs. Of course, certain slips are possible, but looks like 2019 will be the year when EUV will be here. In fact, keeping in mind that both TSMC and Samsung are already talking about their second-gen EUV technologies (which they call 5 and 6 nm) that will use more EUV layers, it looks like the foundries are confident of the ASML TwinScan NXE manufacturing tools (as well as of the Cymer light source, pellicles, photoresists, etc.) they are going to use.

10 nm: Samsung Is Shipping, TSMC Is Steady Beyond 10 nm at Samsung: 8 nm and 6 nm
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  • vladx - Friday, May 5, 2017 - link

    Yep I'm skeptical about a software development revolution, I think focusing on better computer architectures has a much better outlook. Reply
  • melgross - Saturday, May 6, 2017 - link

    Well, there's the question of whether we can get a revolutionary computer architecture these days. It not easy. So we're still looking at cisc vs risc. Maybe we need to go more risc and less cisc. Pretty much everything is some combo of the two. Reply
  • ABR - Sunday, May 7, 2017 - link

    No revolution, but technology has been and will continue advancing here for a long time. Higher-level languages and object-oriented programming making larger projects possible. Evolution in UI frameworks and asynchronous programming (cutting edge in mobile frameworks). Hardware virtualization, network definition migrating to software, and environment encapsulation (e.g., Docker), simplifying resource management. Frameworks like OpenGL, EX, Metal bridging the gap between graphics and graphics hardware. Libraries like Caffe and TensorFlow doing the same for neural networks and learning software.

    Also engineering tools and techniques. Distributed version control systems for source code management. Suites like dpkg or maven for handling dependencies. Team and process practices like the family of Agile techniques.

    The sophistication and sheer amount and ubiquity of software applications in our lives today depends just as much on all of these things as on faster, lower power hardware.
    Reply
  • boeush - Saturday, May 6, 2017 - link

    Once we reach the absolute quantum limits of 2d scaling, we will be looking at alternative materials (graphene, nanotubes, diamond, III-IV chemistry, etc) for better power and frequency scaling. At the same time, 3D stacking of 2D layers by the dozens, then hundreds, then thousands. At the same time, advanced heat dissipation tech (graphene/nanotubes/diamond could serve double duty there), as well as (at least for non-portable devices) refrigeration not just for overclocking but for normal operation. Maybe even look into superconducting chips/interconnects using high-Tc materials, immersed in liquid Nitrogen... There's also research into molecular computing. And, of course, you can always trade off generality against special purpose accelerator ASICs that can provide many-orders-of-magnitude speedup vs conventional processors on same node in specific tasks: and the more compact the node, the more of these various narrow-use circuits you can affordably cram onto a single chip... Reply
  • melgross - Saturday, May 6, 2017 - link

    Sure, there are a lot of technologies out there. But most are just impractical, or just too expensive, and complex. We've has liquid cooling for some time, but do most people really want that? What about notebooks? Can't really be done.

    Other technologies have been considered for a couple of decades but as so expensive that envelope mainframe CPUs can't use them.

    Most of these technologies can be used for every high end use, because of expense, effectiveness, and even power draw. But that's just for the top 0.1% of computing. What about the rest of us?
    Reply
  • ironargonaut - Monday, May 8, 2017 - link

    You mean like when they said that the physics of light would prevent any geometries less then 193nm? Sorry, but the "wall" that was going to end CPU density increases has been broken so many times, that I won't believe it till I see it. Of course just because all those predictions where wrong doesn't mean yours is. Cheers. Reply
  • Gich - Friday, May 5, 2017 - link

    Some time ago I dig up this:

    "14/16nm":
    Intel ~13.4nm - from Broadwell to Coffee Lake, Atom x5/x7
    Samsung/GFo ~16.6nm - AMD Zen and Rx400/500, nVidia 1050, SD 620/820, Exynos 7/8, Apple A9
    TSMC ~18.3nm - nVidia 1060+, Apple A9/10

    "10nm":
    Intel ~9.5nm - Cannonlake
    TSMC ~11.3nm - Helio X30, Kirin 970, Apple A10X
    Samsung ~12.0nm - SD835, Exynos 9
    Reply
  • Gich - Friday, May 5, 2017 - link

    "7nm":
    Intel ~6.7nm
    TSMC/GF ~8.2nm
    Samsung ~8.4nm
    Reply
  • smalM - Monday, May 8, 2017 - link

    TSMC ~18.3nm - that's 16FF which was never used for mass production but is always used by Intel for comparison... Reply
  • helvete - Thursday, July 20, 2017 - link

    Intel paper, intel's point of view. Reply

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