Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV

As noted previously, TSMC’s 7 nm node will be used by tens of companies for hundreds of chips targeting different applications. Initially, the company plans to offer two versions of the manufacturing technology: one for high-performance, and one for mobile applications, both of which will use immersion lithography and DUV. Moreover, eventually TSMC intends to introduce a more advanced 7nm fabrication process that will use EUV for critical layers, taking a page from GlobalFoundries’ book (which is set tp start 7 nm with DUV and then introduces second-gen 7 nm with EUV).

TSMC’s first-generation CLN7FF will enter risk production in Q2 2017 and will be used for over a dozen of tape outs this year. It is expected that high-volume manufacturing (HVM) using the CLN7FF will commence in ~Q2 2018, so, the first “7-nm” ICs will show up in commercial products in the second half of next year. When compared to the CLN16FF+, the CLN7FF will enable chip developers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60% or increase frequency by 30% (at the same complexity).

The second-generation 7 nm from TSMC (CLN7FF+) will use EUV for select layers and will require developers to redesign EUV layers according to more aggressive rules. The improved routing density is expected to provide ~10-15-20% area reduction and enable higher performance and/or lower power consumption. In addition, production cycle of such chips will get shorter when compared to ICs made entirely using DUV tools. TSMC plans to start risk production of products using its CLN7FF+ in Q2 2018 and therefore expect HVM to begin in H2 2019.

Advertised PPA Improvements of TSMC's CLN7FF Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  7FF
vs
16FF+
7FF
vs
10FF
7FF EUV
vs
7FF
5FF EUV
vs
7FF EUV
Power 60% <40% 10% lower
Performance 30% ? lower higher
Area Reduction 70% >37% ~10-15-20% tangible
HVM Start ~Q2 2018 - ~H2 2019 ~H2 2020

As it turns out, all three leading foundries (GlobalFoundries, Samsung Foundry and TSMC) all intend to start using EUV for select layers with their 7 nm nodes. While ASML and other EUV vendors need to solve a number of issues with the technology, it looks like it will be two years down the road before it will be used for commercial ICs. Of course, certain slips are possible, but looks like 2019 will be the year when EUV will be here. In fact, keeping in mind that both TSMC and Samsung are already talking about their second-gen EUV technologies (which they call 5 and 6 nm) that will use more EUV layers, it looks like the foundries are confident of the ASML TwinScan NXE manufacturing tools (as well as of the Cymer light source, pellicles, photoresists, etc.) they are going to use.

10 nm: Samsung Is Shipping, TSMC Is Steady Beyond 10 nm at Samsung: 8 nm and 6 nm
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  • Lodix - Friday, May 5, 2017 - link

    Samsung's 10nmLPP has a 15% reduction in power consumption compared to the LPE version.

    Also the 10nmLPE numbers about performance and power 27/40% are compared to the previous 14nmLPE not the Plus version.
    Reply
  • Lodix - Friday, May 5, 2017 - link

    And the 10nmLPU version is aimed to Area reduction. Reply
  • Anton Shilov - Friday, May 5, 2017 - link

    Thank you for the corrections. You are right about the 10LPP, they made and appropriate announcement a couple of weeks ago, but somehow I've missed it. Fixed.

    Regarding the 10LPE vs 14LP*, I am not sure.

    They state the following:

    "Samsung’s new 10nm FinFET process (10LPE) adopts an advanced 3D transistor structure with additional enhancements in both process technology and design enablement compared to its 14nm predecessor, allowing up to 30-percent increase in area efficiency with 27-percent higher performance or 40-percent lower power consumption."

    http://www.anandtech.com/show/10765/samsung-10nm-m...

    If you look at the picture there (http://images.anandtech.com/doci/10765/dac.png), they mention ~30% performance increase at the same leakage power, which can considered as 27%... But if you happen to see some more up to date slides from Samsung, please link them.

    As for the 10LPU, I guess, they are going to make an announcement in late May.
    Reply
  • Lodix - Friday, May 5, 2017 - link

    I see the arrow joining the 14nmLPE version with 10nmLPE. Reply
  • Lodix - Saturday, May 6, 2017 - link

    In this pdf from Samsung they specified that the improvements stated are from 14nmLPE and not from 14nmLPP.

    https://www.semiwiki.com/forum/attachments/f293/18...
    Reply
  • MajGenRelativity - Friday, May 5, 2017 - link

    I know AMD will be using GF 7nm for their GPUs after Vega 10/11, but I wonder what NVIDIA will be using after this current Pascal generation. Does anyone have any clues? Reply
  • haukionkannel - Friday, May 5, 2017 - link

    If They Are vice They use at least two different distributors just like Apple. Reply
  • melgross - Saturday, May 6, 2017 - link

    Apple has moved away from that model. I doubt they wanted to do it, but neither Samsung nor TSMC could produce all the SoCs they needed that year, so they had to.

    It's also interesting to note that while Apple had to tune their designs to both processes, the TSMC 16nm was 20% more efficient than the Samsung 14nm process. We saw results of those tests either here or on arstechnica, I don't remember which now. But the total device efficiency advantage was under 5% once everything was taken together.

    But still, it shows that we can't go by theory when extrapolating these supposed numbers to the real world. I'd still rather see Apple on intel.
    Reply
  • The_Assimilator - Friday, May 5, 2017 - link

    I would be extremely surprised if it was anyone except TSMC. Especially since TSMC has just announced 10nm is ready for H2 this year - which, not coincidentally, is when NVIDIA is rumoured to drop the first Volta products.

    The only GPU that NVIDIA has ever sourced from a company other than TSMC is GP107 from Samsung at 14nm. Even though Sammy's 14nm node is worse than TSMC's 16nm, GP107 is such a (relatively) small and simple chip that it didn't really matter. We'll probably see a similar story with Volta: TSMC gets the big Pascals, Samsung gets the small ones.

    There is, of course, always the possibility that NVIDIA will stick with the now-mature (and cheaper) 16nm for Volta - I imagine it will depend on whether Volta is more (10nm) or less (16nm) powerful clock-for-clock compared to Pascal.
    Reply
  • Kevin G - Sunday, May 7, 2017 - link

    nVidia has been flirting with Samsung of late. I doubt they'd just exclusively to Samsung but they'll likely continue to have small/medium chip there as a testing vehicle if they need to quickly switch their entire line up over. Reply

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