Beyond 10 nm at TSMC: 7 nm DUV and 7 nm EUV

As noted previously, TSMC’s 7 nm node will be used by tens of companies for hundreds of chips targeting different applications. Initially, the company plans to offer two versions of the manufacturing technology: one for high-performance, and one for mobile applications, both of which will use immersion lithography and DUV. Moreover, eventually TSMC intends to introduce a more advanced 7nm fabrication process that will use EUV for critical layers, taking a page from GlobalFoundries’ book (which is set tp start 7 nm with DUV and then introduces second-gen 7 nm with EUV).

TSMC’s first-generation CLN7FF will enter risk production in Q2 2017 and will be used for over a dozen of tape outs this year. It is expected that high-volume manufacturing (HVM) using the CLN7FF will commence in ~Q2 2018, so, the first “7-nm” ICs will show up in commercial products in the second half of next year. When compared to the CLN16FF+, the CLN7FF will enable chip developers to shrink their die sizes by 70% (at the same transistor count), drop power consumption by 60% or increase frequency by 30% (at the same complexity).

The second-generation 7 nm from TSMC (CLN7FF+) will use EUV for select layers and will require developers to redesign EUV layers according to more aggressive rules. The improved routing density is expected to provide ~10-15-20% area reduction and enable higher performance and/or lower power consumption. In addition, production cycle of such chips will get shorter when compared to ICs made entirely using DUV tools. TSMC plans to start risk production of products using its CLN7FF+ in Q2 2018 and therefore expect HVM to begin in H2 2019.

Advertised PPA Improvements of TSMC's CLN7FF Nodes
Data announced by TSMC during conference calls, press briefings and in press releases
  7FF
vs
16FF+
7FF
vs
10FF
7FF EUV
vs
7FF
5FF EUV
vs
7FF EUV
Power 60% <40% 10% lower
Performance 30% ? lower higher
Area Reduction 70% >37% ~10-15-20% tangible
HVM Start ~Q2 2018 - ~H2 2019 ~H2 2020

As it turns out, all three leading foundries (GlobalFoundries, Samsung Foundry and TSMC) all intend to start using EUV for select layers with their 7 nm nodes. While ASML and other EUV vendors need to solve a number of issues with the technology, it looks like it will be two years down the road before it will be used for commercial ICs. Of course, certain slips are possible, but looks like 2019 will be the year when EUV will be here. In fact, keeping in mind that both TSMC and Samsung are already talking about their second-gen EUV technologies (which they call 5 and 6 nm) that will use more EUV layers, it looks like the foundries are confident of the ASML TwinScan NXE manufacturing tools (as well as of the Cymer light source, pellicles, photoresists, etc.) they are going to use.

10 nm: Samsung Is Shipping, TSMC Is Steady Beyond 10 nm at Samsung: 8 nm and 6 nm
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  • Azethoth - Friday, May 5, 2017 - link

    This is exciting news. The existence of GigaFabs means we must be getting close to the first MegaFab! Reply
  • ishould - Friday, May 5, 2017 - link

    You mean TeraFab? Reply
  • LuckyWhale - Tuesday, May 9, 2017 - link

    I wish Anton would work more on his writing or get a better editor. He writes English so mechanically and itis painfully obvious English is nowhere near his first tongue. I used to follow him at Xbitlabs. Great content but poor writing! sorry. Reply
  • ABR - Thursday, May 11, 2017 - link

    Hmm, normally I'm a stickler about this stuff but with Anton's articles I guess I'm usually so immersed in the content that I don't notice anything! Reply
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  • darkich - Wednesday, May 10, 2017 - link

    Soo..no 7nm on Intel's roadmap?
    Seems like Samsung, GF and TSMC are on their way to leave it in the dust
    Reply
  • peevee - Friday, May 12, 2017 - link

    The "nodes" are just pure lies at this point. 45nm doubled gate density of 65nm, as expected. 10nm chips should have 20 times more transistors per area unit compared to 45nm. They are not even close. And there is nothing which is really 10nm, even a feature as simple as metal pitch is 40-50nm. Reply
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