This week TSMC has disclosed its full quarterly financial results for Q1 2021. In those results the company often explains where the revenue demand is for its technologies, and the financial split the demand brings. This number is not correlated to wafer production (although TSMC provides an overall number too), given that smaller process nodes have a per-wafer premium, but it does indicate where the demand is in the market right now. As perhaps to be expected, 7nm takes top billing, however a couple of interesting numbers come out of the data.

The headline numbers from TSMC’s financial disclosures are that the company made $12.92 billion USD net revenue in Q1 2021, up 1.9% from quarter-to-quarter and up 25% year-on-year. This translates to a 52.4% gross margin, which is down 1.6% Q-on-Q and up 0.6% YoY. TSMC shipped 3.36 million wafers this quarter (based on 12-inch equivalent wafers, because some production is 8-inch), or about 1.12 million per month, 8% more per month than the 2020 average.

This quarter TSMC has hit record wafer production, some 50% higher than its recent Q1 2019 low point. In Q1 2019, TSMC had low demand for high-end smartphones, low customer demand due to oversupply/inventory digestion, and Q1 is typically lower seasonally anyway. But as we can see from the historical 5-year graph, traditional production for TSMC has been around 2.5-2.7m wafers per quarter.

It is only recently that TSMC is pushing out over 3m wafers per quarter, indicating a good shift in demand as we are seeing of late. This is buoyed by TSMC’s newest Fab 18 facility which went into 5nm risk production in Q2 2019, and at full production is expected to manufacture 1 million to 1.2 million 12-inch wafers per year.

This uptick in wafer shipments has had a net positive in net revenue as well.

We see a similar dip in revenue as we did with wafers in Q1 2019, but the recent highs from Q3 2020 onwards are set to continue, with TSMC making $12.92 billion USD for Q1 2021 with a 52.4% gross margin. TSMC indicates that the lower gross margin was partly down to a lower level of utilization in its fabs (likely for upgrades/repairs than lack of demand), as well as an unfavourable exchange rate. For perspective, TSMC holds $13.42 billion USD in net cash reserves, down from Q4 due to an increase in short-term loans and issuance of corporate bonds, but has a cash position of $23.47 billion USD.

As for where the revenue comes from, for the second straight quarter, in Q1 2021 7nm and 5nm combined accounted for almost 50% of the company-wide revenue. 7nm actually increased its revenue share, while 5nm revenue reduced.

7nm accounts for 35% of all revenue, with 5nm now at 14%. This might seem odd, however TSMC has very few customers with 5nm designs, but plenty for 7nm, suggesting that TSMC is able to have customers bid against each other (along with increasing wafer output). For the last few quarters, reports about TSMC’s 7nm lead time for products, from order to production to shipment, have been extending due to the increased demand. Note that TSMC’s most advanced packaging technologies, such as CoWoS, are typically used in conjunction with 7nm or 16nm silicon, so those revenues are likely in those respective segments as well.

Recently TSMC has stated that it plans to spend $100B over the next three years to increase capacity leading-edge capacity, which includes the $25B-$28B it had already planned for 2021, with $12B of that going onto a factory in Arizona. To put that in perspective, TSMC’s Fab 15 which currently produces 12-inch wafers on 7nm, cost $9.3 billion in 2010, and has the capacity for ~100,000 wafer starts per month.

Revenue from 16nm is decreasing, now going below 15% for a couple of quarters, and showcasing that TSMC is making as much money from 16nm as it is from 5nm and 90nm+ older process nodes.

Also on this breakdown of process nodes, we can see that 20nm has bit the bullet, and now rounds to 0% of TSMC’s revenue. Both 20nm and 10nm are now listed at 0% as companies that produced hardware on these nodes are coming to the end of replacement life cycles for those products.

Demand for the older process nodes is still strong, with 28nm and above being 37% of the company revenue, which combined is more than 7nm revenue. Lots of fundamental electronics still require these process nodes, such as high voltage components, high thermal support/long life cycle hardening, or radio frequency silicon that is mature and low cost. Even TSMC’s interposer technology is manufactured on these process nodes, showcasing that the future is going to be a mix of old and new.

Also on TSMC’s disclosure is revenue by platform. The two major markets here are smartphone (45% by revenue) and high-performance computing (35% by revenue), which have consistently been about 80% of the total revenue for TSMC for over a year. The other 20% is taken up by IoT (9%), Automotive (4%), and others (7%).

Full details can be found on TSMC’s Investor Relations website.

From AnandTech’s perspective, we covered TSMC’s Tech Day 2020 disclosures in late August, covering the following topics:

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  • FrankSchwab - Thursday, April 15, 2021 - link

    Building an IC is a combination of costs, and sometimes the older nodes give you the cheapest costs per die. In general, you buy wafers from the fab (the fab doesn't really care what you're putting on the wafer) - on older nodes the wafers are cheaper, on newer nodes they're a lot more expensive. If you get a lot more die per wafer on the newer node, it may be cheaper to use the new process; if you don't, it doesn't make sense.
    Newer, smaller nodes let you pack on a lot more digital circuitry (or, conversely, let you make your die smaller, and thus cheaper). However, things like analog circuitry don't scale well - an op-amp at 55 nm isn't any smaller than an op-amp at 20 nm. This is also true for I/O pads on the die.
    Things like CPUs, GPUs, and RAM are great fits for new process nodes - they're digital and they scale well so the astronomical wafer costs are balanced by the astronomical number of additional transistors you can lay down. Analog ICs are really comfortable at ancient technology nodes - 130 and 180 nm have excellent analog characteristics, and newer process nodes don't make the die any smaller but do make them eye-wateringly more expensive. Microcontrollers live in the middle - we built an ASIC 5 years ago that was roughly 50% analog, and 50% digital (200 MHz ARM with RAM/Flash, etc), and it turned out that, at the volume we were producing, 40 nm was the sweet spot with the lowest die cost.
    Reply
  • dwillmore - Thursday, April 15, 2021 - link

    One suggestion for an addition to this informative article is maybe a table showing the lifetime of the different processes. When did they first ship risk production to when they dropped below 1% or some other criteria. Reply
  • Kamen Rider Blade - Thursday, April 15, 2021 - link

    I'm surprised nobody has stuff manufacturing on TSMC 10nm & 20nm.

    I kind think of plenty of supporting pieces on a MoBo to manufacture on 10nm and 20nm.
    Reply
  • DanNeely - Thursday, April 15, 2021 - link

    some of TSMC's nodes are intended to be long term support nodes that last for many years, others are short termers intended for companies continually chasing the latest and greatest. Most of the time the short term ones are variants rolled up into one of the larger reporting buckets with at least one long term process as well. 10 didn't have a long term version which is why they quickly faded out. Looking at semi-wiki's longer term chart, it looks like 20 was largely superseded by/rolled into 16, before briefly popping up again as a sliver again when it was split out after being largely retired. Reply
  • Zoolook - Tuesday, April 20, 2021 - link

    IIRC TSMC's 20nm wasn't a real node shrink, it was basically 28nm with FinFET, it was rather quickly replaced with their 16 nm which was developed for FinFET from the start. It was never a great node, more of a stopgap to try to catch up to Intel at the time. Reply
  • FrankSchwab - Thursday, April 15, 2021 - link

    >>> I'm surprised nobody has stuff manufacturing on TSMC 10nm & 20nm.
    Probably a combination of reasons.
    The customers (Intel, AMD, NVidia, etc) who could afford the mask costs for 10/20, and need the performance/logic density, of those nodes are the same customers who can afford the mask costs for 7nm, and need 7 nm performance and logic density. They need it, they can afford it, they move.

    Almost everyone else can get by with larger, cheaper nodes. Sure, they COULD transition to 20 nm now that the 20 nm fabs are empty and 20 nm wafers have gotten cheaper, but they'd have to redesign their chip ($20-50M USD or more) and build expensive new masks, and it's likely that the cost savings just aren't there for them.
    Reply
  • Kamen Rider Blade - Thursday, April 15, 2021 - link

    I'm thinking pieces like AMD's Chipset can be made on 20nm & 10nm.

    https://en.wikipedia.org/wiki/List_of_AMD_chipsets...
    -> 300/400 series chipsets are made using 55 nm
    -> The X570 chipset is a repurposed Matisse IO die made using the 14 nm Global Foundries process

    Imagine if AM5's next generation Chipsets were made on 20nm / 10nm.

    The budget one can go on 20nm while the Top Tier Chipset can go to 10nm.

    That would be a tremendous improvement in terms of Power Efficiency/Transistor Density/PCIe Lanes you can slap in to AM5
    Reply
  • valinor89 - Friday, April 16, 2021 - link

    The IO die was made using 14nm because by nature IO scales poorly with shrinking nodes, I would not expect major gains in eficiency from it going to 7 nm, and there is no point in going to 10nm because AFAIK TSMC transitioned that production capacity to 7 nm. I doubt there exist any iddle equipment just for 10nm. Reply
  • nandnandnand - Friday, April 16, 2021 - link

    Rumor is that Zen 4 desktop will have a 6nm I/O die.

    It doesn't scale as well, but it is better.
    Reply
  • FreckledTrout - Monday, April 19, 2021 - link

    It would be beneficial in very lower power devices to shave some IO die power usage off. Reply

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