The AMD team surprised us here. What seemed like a very par-for-the-course Computex keynote turned into an incredible demonstration of what AMD is testing in the lab with TSMC’s new 3D Fabric technologies. We’ve covered 3D Fabric before, but AMD is putting it to good use by stacking up its processors with additional cache, enabling super-fast bandwidth, and better gaming performance. That’s the claim at any rate, and AMD showcased its new demo processor on stage at Computex. Here’s a deeper run-down into what it actually is.

3D Chiplets: The Next Step

AMD announced it was looking into 3D stacking technologies with ‘X3D’ back in March 2020 at its Financial Analyst Day, with a very odd diagram showing a chiplet processor with what looked like stacks of HBM or some sort of memory around the outside. At the time AMD said it was a mix of 2.5D and 3D packaging technologies enabling 10x bandwidth density or higher. The ‘X’ in ‘X3D’ was meant to stand for Hybrid, and the technology was set for ‘the future’. Since then TSMC has announced its 3D Fabric line of technologies, a broad name for its combination of 2.5D and 3D integration offerings.

Today AMD presented the first stage of its 3D chiplet journey. The first application is a stacked cache on top of a standard processor chiplet. On stage, Lisa Su showcased one of AMD’s Ryzen 5000 dual-chiplet processors with Zen 3 cores. On one of the compute chiplets, a 64 MB SRAM built on TSMC’s 7nm was integrated on the top, effectively tripling the amount of cache that the cores have access to.

That means that the original Ryzen 5000 chiplet, with eight cores having access to 32 MB of L3 cache, now becomes an eight-core complex with access to 96 MB of L3 cache. The two dies are bonded with Through Silicon Vias (TSVs), passing power and data between the two. AMD claims that the total bandwidth of the L3 cache increases to beyond 2 TB/sec, which would technically be faster than the L1 cache on the die (but with higher latency).

As part of the chip diagram, the TSVs would be direct copper-to-copper bonding. The cache die is not the same size as the core complex, and as a result additional structural silicon is needed to ensure that there is equal pressure across both the bottom compute die and the top cache die. Both dies are thinned, with the goal to enable the new chiplet in the same substrate and heatspreader technology currently in use in Ryzen 5000 processors.

The prototype processor shown on stage had one of its chiplets using this new caching technology. The other chiplet was left as standard to show the difference, and the one chiplet that had the cache die ‘exposed’ made it obvious and comparable with the regular non- integrated chiplet. CEO Dr. Lisa Su said that the 64 MB SRAM in this case is a 6mm x 6mm design (36 mm2), which puts it at just under half the die area of a full Zen 3 chiplet.

In a full product Lisa explained that all the chiplets would have the stacked cache enabled, for 96 MB of cache per chiplet, or 192 MB total for a processor like this that has 12 or 16 cores.

As part of the technology, it was explained that this packaging enables a >200x interconnect density compared to regular 2D packaging (which is something we already know from HBM stacking), a >15x density increase compared to microbump technology (a shot straight across the bow of Intel’s Foveros), and >3x better interconnect efficiency compared to microbumps. The TSV interface is a direct die-to-die copper interconnect, meaning that AMD is using TSMC’s Chip-on-Wafer technology. Dr Su claimed on stage that these features make this the most advanced and flexible ‘active-on-active’ chip stacking technology in the industry.

As for performance demonstrations, AMD compared a before and after using Gears of War 5. On one side was a standard Ryzen 9 5900X 12-core processor, while the other was a prototype using the new 3D V-Cache built upon a Ryzen 9 5900X. Both processors were fixed at 4 GHz, and paired with an un-named graphics card.

In this scenario the comparison point is that one processor has 64 MB of L3 cache, while the other has 192 MB of L3 cache. One of the selling points of Ryzen 5000 processors was the extended L3 cache available to each processor to help with gaming performance, and moving that up to 96 MB per chiplet extends that advantage even further, with AMD showing a +12% FPS gain (184 FPS vs 206 FPS) with the increased cache size at 1080p. Over a series of games, AMD claimed +15% average gaming performance:

  • DOTA2 (Vulkan): +18%
  • Gears 5 (DX12): +12%
  • Monster Hunter World (DX11): +25%
  • League of Legends (DX11): +4%
  • Fortnite (DX12): +17%

This is not an exhaustive list by any means, but it makes for interesting reading. AMD’s claim here is that a +15% bump is akin to a full architecture generation jump, effectively enabling a rare improvement through philosophical design differences. Here at AnandTech we would like to note that as it becomes harder to drill down into new process nodes, philosophical design enhancements might become the main driver of future performance.

AMD says that it has made great strides with the technology, and is set to put it into production with its highest-end processors by the end of the year. It wasn’t stated on what products it would be coming to, whether that was consumer or enterprise. Apropos of this, AMD has said that Zen 4 is set for launch in 2022.

The AnandTech Analysis

Well that was unexpected. We knew that AMD was going to be investing in TSMC’s 3D Fabric technology, but I guess we didn’t expect it to be this soon or with a demo on a desktop processor first.

Starting with the technology, this is clearly TSMC’s SoIC Chip-on-Wafer in action, albeit with only two layers. TSMC has demonstrated twelve layers, however those were non-active layers. The problem with stacking silicon is going to be in the activity, and subsequently thermals. We’ve seen with other TSV stacked hardware, like HBM, that SRAM/memory/cache is the perfect vehicle for this as it doesn’t add that much to the thermal requirements of the processor. The downside is that the cache you stack on top is little more than just cache.

This is where AMD and Intel’s stacking differs. By using TSVs rather than microbumps, AMD can get greater bandwidth and power efficiency out of TSVs, but also stack multiple chiplets high if needed. TSVs can carry power and data, but you still have to design around the two for cross signaling. Intel’s Foveros technology, while it is also 3D stacking, it relies on microbumps between the two chiplets. These are bigger and power-hungry, but allow Intel to put logic on both the lower die and upper die. The other element is thermals – usually you want the logic on the top die to manage the thermals better as it is close to the heatspreader/heatsink, but moving logic further away from the substrate means that power has to be transported up to the top die. Intel is hoping to mix microbumps and TSVs in upcoming technologies, and TSMC has a similar roadmap for the future for its customers.

Moving to the chiplet itself, it was claimed that the 64 MB L3 cache chiplet is 6mm x 6mm, or 36 mm2, and is built on TSMC 7nm. The fact that it is built on TSMC 7nm is going to be a critical point here – you might think that a cache chiplet might be better suited to a cheaper process node. The tradeoff in cost is power and die area (yield at such a small die size isn’t worth considering). If AMD is to make these cache chiplets on TSMC 7nm, then that means a Zen 3 with additional cache requires 80.7 mm2 for the Zen 3 chiplet as normal, then another 36 mm2 for the cache, effectively requiring 45% more silicon per processor. While we’re currently in a silicon shortage, this might have an effect on how many processors are made available for wider use. This might be why AMD said it was looking at ‘highest-end’ products first.

Now adding 64 MB of cache to a chip that already has 32 MB of L3 cache isn’t as straightforward as it seems. If AMD is directly integrating it as an adjacency to the L3 cache, then we have a dual-tiered L3 cache. Likely accessing that 64 MB requires more power, but that provides greater bandwidth. It would depend on the workload if the regular 32 MB is enough, compared to the extra 64 MB provided by the stacked die. We could see the extra 64 MB seen as an equivalent L4 cache, however the issue here is that in order for that extra 64 MB to go out to main memory, it has to pass through the main chiplet under it. That’s an additional power draw worth noting. I am very interested in seeing how the memory profile from the perspective of a core comes out with this extra chiplet, and how AMD is integrating that into the structure. AMD has stated that it is an SRAM-based design, so unfortunately it isn’t anything fancy like persistent memory, which would have been a whole different design ethos. By sticking to SRAM it means that at least it can seamlessly provide performance uplifts.

On the performance, we’ve seen L3 cache depth improve gaming performance, both for discrete and integrated gaming. However, increased L3 cache depth doesn’t do much else for performance. This was best exemplified in our review of Intel’s Broadwell processors, with 128 MB of L4 cache (~77 mm2 on Intel 22nm), wherein the extra cache only improved gaming and compression/decompression tests. It will be interesting to see how AMD markets the technology beyond gaming.

Finally, interception into the mainstream - AMD says that it is ready to start integrating the technology into its high-end portfolio with production at the end of the year. AMD has said that Zen 4 on 5nm launch is in 2022. Based on previous timescales, we have predicted that AMD’s next processor family is roughly a Feb 2022 launch. Whether that would be Zen 4 it’s unclear at this point, but also Zen 4 is on 5nm and AMD is showcasing this 3D V-Cache on 7nm. Whether AMD has plans to monetize this feature on 7nm, or whether it might combine a 5nm Zen 4 chiplet with a 7nm 64 MB cache chiplet is unclear. It wouldn’t be too difficult to combine the two, however I suspect that AMD might want to push its caching technology into more premium products than Ryzen desktop. We might see special one-off editions as the technology ramps through the stack.

To conclude, I have a number of questions I’d like to ask AMD. I’m hoping that I will get some answers, and if I do, I’ll cycle back with the details.

Update: June 1st:

In a call with AMD, we have confirmed the following:

  • This technology will be productized with 7nm Zen 3-based Ryzen processors. Nothing was said about EPYC.
  • Those processors will start production at the end of the year. No comment on availability, although Q1 2022 would fit into AMD's regular cadence.
  • This V-Cache chiplet is 64 MB of additional L3, with no stepped penalty on latency. The V-Cache is address striped with the normal L3 and can be powered down when not in use. The V-Cache sits on the same power plane as the regular L3.
  • The processor with V-Cache is the same z-height as current Zen 3 products - both the core chiplet and the V-Cache are thinned to have an equal z-height as the IOD die for seamless integration
  • As the V-Cache is built over the L3 cache on the main CCX, it doesn't sit over any of the hotspots created by the cores and so thermal considerations are less of an issue. The support silicon above the cores is designed to be thermally efficient.
  • The V-Cache is a single 64 MB die, and is relatively denser than the normal L3 because it uses SRAM-optimized libraries of TSMC's 7nm process, AMD knows that TSMC can do multiple stacked dies, however AMD is only talking about a 1-High stack at this time which it will bring to market.
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  • davidefreeman - Wednesday, June 2, 2021 - link

    The SRAM chiplet is stacked above the +existing+ L3 cache, specifically to avoid thermal issues. While there is a passive silicon spacer above the logic, it will not add additional heat. Both dies have been thinned, so total thickness hasn't changed. I'd expect thermal transference hasn't significantly increased. They could probably make up for that difference by specifying a higher TDP and a better cooling solution over stock parts, assuming there is even a noticeable difference, Reply
  • zodiacfml - Tuesday, June 1, 2021 - link

    Brings back memories when they were first with the IMC. If i'm correct, brought 5-8% improvement. This is a different beast though, a very pricey part. Reply
  • msroadkill612 - Tuesday, June 1, 2021 - link

    Which probably means u can bump the Fabric clock speed, which means u can bump DDR 1:1 ram clock speeds.

    I have a problem w/ the automatic assumption that APUs are for peasants.

    I suspect there are many well heeled buyers who see their advantages too, and wont mind a significant premium for advanced examples.
    Reply
  • Mil0 - Thursday, June 3, 2021 - link

    Ever since kaby-lake G I've been wondering why amd didn't do something like that with pure amd. Perhaps they were waiting for this combined with ddr 5. I'd say rdna @5nm + 256MB infinity cache would give amazing perf to the ultrabook format. And although my heels are dressed like a peasant, my laptop preferences are not. Reply
  • msroadkill612 - Tuesday, June 1, 2021 - link

    I hope I am not reposting that AMD are making similar caches for their GPU card's Infinity Fabric Bus.

    Their vision seems to be a much tighter integration between system & GPU resources.

    Taken together:

    recent advances in system ram speed & capacity
    the double bandwidth of pcie 4
    this discussed l3 cache on both of the linked fabric buses

    add up to quite a paradigm shift potential.

    apps like MS Flight Simulator doing a reasonable simulation of 48GB GPU cache on a 16GB gpu card eg.
    Reply
  • TanjB - Tuesday, June 1, 2021 - link

    Your analysis is confused. The direct bonding and the TSVs are different things. Only a fraction of the bonds go the TSVs. The bonds for the L3 data and command signals go directly to the circuits in face to face position, with the direct bonding (aka hybrid bonding) providing a minimal burden on the circuit for best efficiency and low latency.

    The fraction of the bonds which go to TSVs will be carrying power and also IO signals. This is because the cache chip will be on the bottom, and the compute chip reaches through those TSVs to reach the substrate. The compute chip is on top, not on bottom, so that it does not have any TSVs through itself and also so it remains closest to the heat sink.

    The TSVs are etched through the thickness of the cache chip. This is likely only 15 microns or so, but these TSVs are the size and load of microbumps. You cannot have nearly as many TSVs as you can of the signal bonds. When you stack more than to chips you cannot carry anything like the bandwidth, nor the low energy per bit, that are available to the direct signal bonds on the face-to-face pair.

    It is great technology and we will see more of it, but keep a clear view of what it offers.
    Reply
  • Rudde - Tuesday, June 1, 2021 - link

    In the demo, the cache chip is on the top, which can easily be seen from the smaller square shaped bump on one of the chiplets. The slide is even more explicit about it, as it shows the cache in the middle with the cores on the sides with structural silicon on top. Simply put, AMD has the compute die on the bottom with cache on top. Reply
  • davidefreeman - Wednesday, June 2, 2021 - link

    L3 die is above the compute die. Compute uses the most power, so keeping it as-is avoid transferring power a longer distance through TSV's. The L3 die is stacked above +existing+ L3 SRAM, avoiding thermal issues that would occur if stacked over compute logic. Reply
  • SarahKerrigan - Tuesday, June 1, 2021 - link

    Maybe I'm missing something, but are tags stored on the main CPU die like in a lot of off-chip cache implementations? Reply
  • Rudde - Tuesday, June 1, 2021 - link

    I've understood that AMD has the tags between memory banks. You can think of it like stripes of memory banks and tags. Reply

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