The Primer: PCI Express 1.0 vs. 2.0

A serial interface, PCI Express is organized into lanes. Each lane has an independent set of transmit and receive pins, and data can be sent in both directions simultaneously. And here’s where things get misleading. Bandwidth in a single direction for a single PCIe 1.0 lane (x1) is 250MB/s, but because you can send and receive 250MB/s at the same time Intel likes to state the bandwidth available to a PCIe 1.0 x1 slot as 500MB/s. While that is the total aggregate bandwidth available to a single slot, you can only reach that bandwidth figure if you’re reading and writing at the same time.

One of our first encounters with PCI Express was at IDF in 2002

PCI Express 2.0 doubles the bidirectional bandwidth per lane. Instead of 250MB/s in each direction per lane, you get 500MB/s.

Other than graphics, there haven’t been any high bandwidth consumers on the PCIe bus in desktops. Thus the distinction between PCIe 1.0 and 2.0 has never really mattered. Today, both USB 3.0 and 6Gbps SATA aim to change that. Both can easily saturate a PCIe 1.0 x1 connection.

Intel's X58 Chipset. The only PCIe 2.0 lanes come from the IOH.

This is a problem because all Intel chipsets have a combination of PCIe 1.0 and 2.0 slots. Intel’s X58 chipset for example has 36 PCIe 2.0 lanes off of the X58 IOH, plus an additional 6 PCIe 1.0 lanes off the ICH. AMD’s 7 and 8 series chipsets don’t have any PCIe 1.0 slots.

AMD's 890GX doesn't have any PCIe 1.0 lanes

No desktop chipset natively supports both 6Gbps SATA and USB 3.0. AMD’s 8-series brings native 6Gbps SATA support, but USB 3 still requires an external controller. On Intel chipsets, you need a separate controller for both 6Gbps SATA and USB 3.

These 3rd party controllers are all PCIe devices, just placed on the motherboard. NEC’s µPD720200 is exclusively used by all motherboard manufacturers for enabling USB 3.0 support. The µPD720200 has a PCIe 2.0 x1 interface and supports two USB 3.0 ports.

The USB 3 spec calls for transfer rates of up to 500MB/s. Connected to a PCIe 2.0 interface, you get 500MB/s up and down, more than enough bandwidth for the controller. However if you connect the controller to a PCIe 1.0 interface, you only get half that (and even less in practice). It’s not a problem today but eventually, with a fast enough USB 3 device, you’d run into a bottleneck.

The 6Gbps situation isn’t any better. Marvell’s 88SE91xx PCIe 2.0 controller is the only way to enable 6Gbps SATA on motherboards (other than 890GX boards) or add-in cards today.

The interface is only a single PCIe 2.0 lane. The 6Gbps SATA spec allows for up to 750MB/s of bandwidth, but the PCIe 2.0 x1 interface limits read/write speed to 500MB/s. Pair it with a PCIe 1.0 x1 interface and you’re down to 250MB/s (and much less in reality due to bus overhead).

Index The C300 and What About P5x/H5x?


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  • sparkuss - Thursday, March 25, 2010 - link


    I was going to maybe get two C300's for my current build. Do we consumers need to wait for your update before we invest in these?

    We know it died, but I haven't been able to find any other reliability statistics collated anywhere to make a buying decision on.
  • sparkuss - Thursday, March 25, 2010 - link

    Sorry, I missed the Update link in the upper corner. Reply
  • vol7ron - Thursday, March 25, 2010 - link

    Great review. Not much to be said. There was a little bit of puffery at the end, in AMDs favor.

    I'm sure most companies have faster controllers/BIOSs to be released. Rather than saying AMD is something to look out for, for some reason I'd think Intel would have something greater.

    As you mentioned, the on-die controller should have lower latencies - could you ask them about this? Perhaps some of the PCI bandwidth is being chewed up by something else, or perhaps the latencies are too low, causing a check/repeat bottleneck? (or maybe this a marketing ploy to release something faster in the future)
  • Dzban - Thursday, March 25, 2010 - link

    Because AMD has native 6Gbps and they are improving drivers. With intel chipsets you can't phisicly increase speed further. Reply
  • vol7ron - Thursday, March 25, 2010 - link

    I don't like how Intel switches between [Mb/s & Gb/s] and [MB/s & GB/s]. It'd be nicer to not have to translate 480Mbps into 60MB.

    I guess the issue was at first past I almost equated the 480Mb/s to the 500MB/s right under it.
  • jejeahdh - Thursday, March 25, 2010 - link

    You should not type dates in that format, and if you had an editor, he or she should absolutely stop you from doing such things. People have expectations. You might think it's no worse than the ever-present traditional ambiguous formats of the US and Europe (m/d/yy(yy), d/m/yy(yy)) which are bad enough, but at least it's an old and well recognized problem that people are used to living with, so long as it uses slashes. People with knowledge of standards, though, use dashes for ISO date format, yyyy-mm-dd which is also perfectly sortable. By mixing and matching styles haphazardly, you're only propagating the notion that anything goes, causing people to stop and wonder for 12 days out of every month. If you're deliberately adopting the style commonly used in the Netherlands (I had to look it up) and advocating its use for an international audience, I cannot imagine why.

    I know it seems crazy to harp on this and I kind of agree . . . but I am just so surprised to see it here, written by a detail oriented technically minded accomplished writer.
  • strikeback03 - Friday, March 26, 2010 - link

    If this is in response to the IOMeter build, that might be the way it was named by its creator, not Anand. Also, I would imagine 6-22-2008 is m-dd-yyyy Reply
  • assassin37 - Thursday, March 25, 2010 - link

    Hey Anand, Why isn't the X-58 gigabyte native 6gbs board on the write benchmarks? Reply
  • assassin37 - Thursday, March 25, 2010 - link

    never mind I read why, legacy mode Reply
  • vailr - Thursday, March 25, 2010 - link

    Intel releases SSD friendly AHCI/RAID driver:">

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